ASIC / VLSI - Staff Engineer, Timing & Synthesis Semtech - Bhubanswar

Job description

Responsibilities:

Candidate will be responsible for synthesis & STA setup, full chip timing analysis, timing eco closure. Responsibilities also include supporting backend design team to tape out of the full chip. Candidate should also possess excellent communication skills to interact with external customers and cross site teams within company. Candidate will get an opportunity to work in RTL development and micro-architecture of digital blocks

Desired Skills and Experience

Requirements:

• Expertise in Synthesis, Static timing analysis and Equivalence
• Checking (LEC) using synopsys/cadence tools.
• Experience in timing constraints development & validation is a must.
• Experience in developing & validating the functional & test-mode timing constraints is also must.
• Familiarity with ASIC design flows for deep sub-micron technologies. 40nm and 28nm will be preferable. 
• Knowledge of DFT/ATPG/MBIST will be a plus point.
• Any exposure to Synopsys Lynx flow will be preferable.
• Knowledge of RTL design and functional simulation will be preferable.

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