single precision floating point multiplication algorithem description for 32 bit

In this video , we explain the floating point multiplication of 32 bit by single precision . We explain complete flow of algo for single precision floating point multiplication . We take so many examples and find the mantissa and exponent for the numbers . finally we show the mantissa and exponent with sign of the answer  .

Xilinx new project design video with AND gate VHDL code

In this video , we explain that how we can design the new project in the Xilinx project navigator . In this video you also get that how we can select the FPGA kit packages in the Xilinx project navigator . In the another section we mention the VHDL coding for the AND gate by use DATA FLOW modeling style . After this we explain the RTL for the AND GATE logic and waveform generation for the AND gate Design . In this video , AND gate all possible conditions are mention and show by the waveform generation . In the end we also explain the floor planer design for AND gate logic .

VLSI basic description

In this video we explain the basics of the VLSI . We describe the difference between front end VLSI and Back end VLSI . In this video we also explain the full form of VLSI . Video explain the transistor level theory for simple AND gate .

In this video we are giving explanation for some given points

1:- what is VLSI  ?
2:- Transistor level theory for IC design ..

single precision floating point mantissa multiplication

In this video we design the program for mantissa multiplications . In this video we are working for single precision floating point representation of mantissa . we also explain the VHDL program for single precision floating point mantissa multiplication . In single precision floating point multiplication 23 bit of mantissa get multiplied by another 23 bit mantissa bits, so in this video firstly we explain that what is the mantissa and then we show that how we can design a VHDL program for single precision floating point mantissa multiplication .

structural modeling in VHDL

In this video we mention the process for design the structural modeling style in VHDL . We are designing a AND gate by use structural modeling style in VHDL . We are using xilinx software for explain structural modeling style in VHDL . We also show the output waveform of the AND gate by use structural modeling style in VHDL .

how to design xor gate by VHDL in XILINX project navigator

This video describe you that how we can design a XOR gate by VHDL. In this we also describe that how we can generate a waveform for XOR gate in XILINX by MODELSIM..

How to install xilinx and modelsim VLSI software

In this video we are telling that how we can install xilinx project navigator & Modelsim 5.4 .  How we can integrate both so that we can check waveform  for all VHDL codes.

integer counter design by Xilinx with VHDL code

this a inter counter by vhdl video . in this video we are describing that how we can design a integer counter by vhdl and how we can see output in waveform .
for this we are using xilinx project navigator 6.1 with installed modelsim 5.4

ENCODER DESIGNING BY VHDL AT XILINX PROJECT NAVIGATOR

it is a video in which we describe that how we can make a vhdl code for a encoder in different modeling style . for this work we are using  xilinx project navigator 6.1 with installed modelsim 5.4 .

AND GATE PROGRAM AT XILINX PROJECT NAVIGATOR BY VHDL

it is a video in which you can easily understand that how we can make a new program xilinx project navigator . it is a and gate program by use of xilinx project navigator.

package decalaration by VHDL xilinx project navigator

In this video we design the package by use of VHDL . package declaration is a mail part of VHDL . We design a package by name of vlsi. In this package we design two function for and gate , or gate . In the program first part we declarer the package with function name and in the program second part declare the package body with function declaration .

single precision floating point mantissa multiplication :-

In this blog we mention the points for single precision floating point precision mantissa multiplication . For single precision floating point multiplication , we have 32 bit .

In single precision floating point multiplication bits explain are given like below

1:- 23 bits for mantissa
2:- 8 bits for exponent
3:- 1 bit sign

so if we combined  all the bits then total bits will come 32 bit .

In the single precision floating point multiplication also work structure :-

Like we have two numbers

X = 10.5
Y = 10.4

Mantissa of X (Mx)(23 bits ) = 10101000000000000000000

How we can find mantissa ?



We have to find the mantissa for the X number . In the number 10.5 we have to break the number in two parts.

10 (before the point )
.5 (after the point )

firstly we have to find the binary number of the 10 . The binary of the 10 is 1010 .
then we have to find the binary number of .5

.5 * 2  = 1.0

So combined 10.5 decimal number binary is 1010.100000000000000000000

now we have to find the mantissa of 10.5 . so we will shift the point towards left .

1.01010000000000000000000 * 2^3 .

In this 01010000000000000000000 is the mantissa of X of 23 bit .

Mx = 01010000000000000000000

Exponent

Ex(exponent ) :- 127+3(from power of 2 ) = 130 = 10000010 (binary )

Sign

If the umber is positive then sign bit will be 0 else sign bit will be 1 .

according to this

Mx(mantissa of x)= 01010000000000000000000
Ex (exponent of y ) = 10000010
Sx (sign of x) = 0

Y= 10.4
My =  01001100110011001100110
Ey = 10000010
Sy = 0

Now we will multiply both the mantissa numbers for find final mantissa number .

Example :-



For design the mantissa multiplication VHDL program see this video :-

Ez = Ex + Ey - 127

For Sz  =  Sx xor Sy

like this we can implement the single precision multiplication .

For any query , please post your query in comment box .