multiplexer design by verilog code

In this video , multiplexer is design by verilog code  . in this video we are using behavioral modeling style in verilog for design multiplexer 2:1 . We are working for always , if else statement for design the multiplexer 2:1 . For design the verilog code of multiplexer 2:1 we are using xilinx project navigator . we also show the waveform at modelsim simulator .

How to install xilinx and modelsim VLSI software

In this video we are telling that how we can install xilinx project navigator & Modelsim 5.4 .  How we can integrate both so that we can check waveform  for all VHDL codes.

multiplexer design by Xilinx with verilog code

In this video , multiplexer is design by verilog code  . in this video we are using behavioral modeling style in verilog for design multiplexer 2:1 . We are working for always , if else statement for design the multiplexer 2:1 . For design the verilog code of multiplexer 2:1 we are using xilinx project navigator . we also show the waveform at modelsim simulator .

binary counter design by verilog in xilinx project navigator

In this video , we are designing a counter for the binary 4 bit numbers . counter is starting from 0000 to 1111 . in this we are using verilog behavioral modeling style . we are using always statement with if else statement .
In this video a binary counter verilog code by use xilinx project navigator from  000o to 1111.

binary counter design by xilinx with verilog code

in this video , we design the binary counter . We are using verilog code for design binary counter . The binary counter is starting from 0000 to 1111. In this video binary counter is not showing the waveform . In this we use $display command for display the counter in modelsim command window .