Xilinx new project design video with AND gate VHDL code

In this video , we explain that how we can design the new project in the Xilinx project navigator . In this video you also get that how we can select the FPGA kit packages in the Xilinx project navigator . In the another section we mention the VHDL coding for the AND gate by use DATA FLOW modeling style . After this we explain the RTL for the AND GATE logic and waveform generation for the AND gate Design . In this video , AND gate all possible conditions are mention and show by the waveform generation . In the end we also explain the floor planer design for AND gate logic .