Approval to establish two Semiconductor Wafer Fabrication Manufacturing Facilities in India
The
Cabinet has approved setting up of two Semiconductor Wafer Fabrication
(FAB) Manufacturing Facilities in India. These FAB units are to be set
up by two business consortia, with the following broad project
parameters:
(i) M/s Jaiprakash Associates Limited (with IBM, USA and Tower Semiconductor Limited, Israel as partners)
a) Project Cost: Rs 34,399 crore
b) Technology: 90/65/45/28 nm
c) Capacity: 40,000 WSPM
d) Location: Yamuna Expressway, Uttar Pradesh
(ii) M/s HSMC Technologies India Pvt. Ltd. (with ST Microelectronics and Silterra Malaysia Sdn. Bhd. as partners)
a) Project Cost: Rs 29,013 crore
b) Technology: 90/65/45/28/22 nm
c) Capacity: 40,000 WSPM
d) Location: Prantij, Gujarat
The Empowered
Committee has been authorized to take all decisions to implement the
FAB projects in furtherance of the decision. The proposed FABs will create direct employment of about 22,000 and indirect employment of about one lakh.
These
FABs will have a big impact on the development of Electronics System
Design and Manufacturing eco-system across the country. This will help
set up a critical pillar required to promote Electronics System Design
and Manufacturing in India. The Semiconductor Wafer Fabrication units
when set up, will stimulate the flow of capital and technology, create
employment opportunities, help higher value addition in the electronic
products manufactured in India, reduce dependence on imports, and lead
to innovation.
The following main incentives will be extended:
i. 25% subsidy on capital expenditure and tax reimbursement as
admissible under Modified Special Incentive Package Scheme (M-SIPS)
Policy.
ii. Exemption of Basic Customs Duty (BCD) for non-covered capital items
iii. 200% deduction on expenditure on R&D as admissible under Section 35(2AB) of the Income Tax (IT) Act.
iv. Investment linked deductions under Section 35AD of the IT Act.
v. Interest free loan of approx. Rs 5124 crore each. (Exact amount to be calculated on Detailed Project Report appraisal.)
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