Job description
Job Description and Requirements
As a Corporate Applications Engineer II, you will contribute to making Synopsys Synplify Pro and Premier synthesis tools a technical and commercial success by helping create specifications and by testing the tool from a user’s perspective in order to improve functionality and quality.
Job Requirement:
- BE or ME with 2 to 3 years of experience in logic design and implementation using FPGAs.
- Should have very good hands on experience in Verilog and/or VHDL.
- Should have good experience in Synthesis, back end flow, FPGA architecture and implementing designs in hardware.
- Exposure to Xilinx/Altera synthesis software is a plus.
- Excellent communication and inter-personal skills, professional attitude and strong desire to succeed.
- Scripting knowledge desirable.
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