Verification Engineer Imagination Technologies - Pune

Job description

• Primary responsibilities will include:
  Experience : 3 to 7 Years
• Development of Verification Environment (VE) / Verification Component (VC) using UVM SV / UVM e
• Writing tests, sequences, functional coverage, assertions and mapping these to Verification plan
• Functional verification of the design and achieve verification goals
• VHDL / Verilog Testbench coding

Required Skills

• An excellent knowledge of digital design verification techniques
• Good knowledge of OVM / UVM methodology and verification language like System Verilog, Specman ‘e’.
• Experience in SoC and/or IP verification using any of the above methodology and language
• Experience in developing VE, UVCs, writing tests, sequences, functional coverage and checks / assertions
• Understanding of VHDL and/or Verilog programming languages.

Desired Skills and Experience

Desirable Skills

• Experience in Peripheral IPs integration verification and/or Verification IP UVCs.
• Expertise with C++ and systemC programming / modeling.
• Experience with scripting language/s like Perl/Python

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