Job description
Job Description :
As a Design Engineer, you will be responsible for · RTL Verilog design · Chip level integration · Work in USB2, USB3 hub protocol · Work in chip level integration · Running RTL and Gate level simulation and debugging · Writing new test cases · FPGA Flow using Xilinx
Job Requirements :
· Bachelor's degree in Electrical Engineering (or equivalent) · 3+ years of experience in frontend design · Experience in Verilog, VHDL (optional) · Good understanding of Digital design · Experience in Linting, Synthesis using Synopsis Design Compiler · Understanding timing analysis using PT (Optional) · Knowledge of Mentor DFT tools (optional) · Knowledge of 8051 or ARM or any other microcontroller · knowledge of USB2, USB3 · Knowledge of APB,AHB · Ability to work on DC,PT,FORMAL synopsis tools · Experience in Make file scripting, Perl scripting · Understanding Low power design
Offer Relocation : Maybe
Apply Now
As a Design Engineer, you will be responsible for · RTL Verilog design · Chip level integration · Work in USB2, USB3 hub protocol · Work in chip level integration · Running RTL and Gate level simulation and debugging · Writing new test cases · FPGA Flow using Xilinx
Job Requirements :
· Bachelor's degree in Electrical Engineering (or equivalent) · 3+ years of experience in frontend design · Experience in Verilog, VHDL (optional) · Good understanding of Digital design · Experience in Linting, Synthesis using Synopsis Design Compiler · Understanding timing analysis using PT (Optional) · Knowledge of Mentor DFT tools (optional) · Knowledge of 8051 or ARM or any other microcontroller · knowledge of USB2, USB3 · Knowledge of APB,AHB · Ability to work on DC,PT,FORMAL synopsis tools · Experience in Make file scripting, Perl scripting · Understanding Low power design
Offer Relocation : Maybe
Apply Now
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