Job description
3.Frontend CAD Methodology/Domain Experts (5+ years VLSI Experience)
Skills:
BS or MS in Electrical or Computer Engineering.
5+ years of experience in Front End CAD (Design/Verification).
Expert in Formal Verification and ECO flows. Good programming/scripting skills (Perl/Tcl)
Familiar with design and verification languages: Verilog, System Verilog, SVA etc.
Ability and drive to understand technology trends and identify gaps in the existing flow, how to prioritize solutions/capabilities and to decide the best way to implement.
Preferably familiar with some front-end EDA tools: HDL simulators (e.g. Questa, VCS, Incisive), design debugging (e.g. Springsoft) etc.
Responsibilities
Basic Qualifications
Education Requirements
Bachelor's, Computer Engineering
Skills:
BS or MS in Electrical or Computer Engineering.
5+ years of experience in Front End CAD (Design/Verification).
Expert in Formal Verification and ECO flows. Good programming/scripting skills (Perl/Tcl)
Familiar with design and verification languages: Verilog, System Verilog, SVA etc.
Ability and drive to understand technology trends and identify gaps in the existing flow, how to prioritize solutions/capabilities and to decide the best way to implement.
Preferably familiar with some front-end EDA tools: HDL simulators (e.g. Questa, VCS, Incisive), design debugging (e.g. Springsoft) etc.
Responsibilities
Basic Qualifications
Education Requirements
Bachelor's, Computer Engineering
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