Job description
Job Function (Briefly describe what the person will do on the job)
- Hands on work in Digital design using RTL - Verilog, VHDL etc
- Should be able to work on digital design from spec to RTL
- Develop and execute Architecture, microarchitecture, Unit level verification etc.
- Assist coverage closure for desgined modules
- Formal equivalence checking
- Must be able to run STA and synthesis and close timing for designed modules pre-layout
- Gate level/Power simulations
- Documentation creation like user guide, design doc etc
- Hands on work in Digital design using RTL - Verilog, VHDL etc
- Should be able to work on digital design from spec to RTL
- Develop and execute Architecture, microarchitecture, Unit level verification etc.
- Assist coverage closure for desgined modules
- Formal equivalence checking
- Must be able to run STA and synthesis and close timing for designed modules pre-layout
- Gate level/Power simulations
- Documentation creation like user guide, design doc etc
Desired Skills and Experience
Skills / Experience (Describe the skills in detail required to do this job)
• Knowledge in one or more: imaging, graphics, video, memory, multimedia domains
• Knowledge in bus protocols - APB, AHB, AXI, and bus interconnects
• Prefer experience in SOC architecture and/or IP
• Experience with top level arch and micro-arch development
• Experience with test coverage assessment
• Experience with Synthesis and running gate level simulations
• Experience using Perl or other UNIX scripting will be an added advantage
• Experience with STA/Timing closure
• Experience with Formal equivalence checking
• Knowledge in one or more: imaging, graphics, video, memory, multimedia domains
• Knowledge in bus protocols - APB, AHB, AXI, and bus interconnects
• Prefer experience in SOC architecture and/or IP
• Experience with top level arch and micro-arch development
• Experience with test coverage assessment
• Experience with Synthesis and running gate level simulations
• Experience using Perl or other UNIX scripting will be an added advantage
• Experience with STA/Timing closure
• Experience with Formal equivalence checking
No comments:
Post a Comment