Online VLSI (Verilog) Project Based Training (03/9/14 )

Online VLSI (Verilog) Project Based Training (03/9/14 ) :-

VLSI EngiTech Pvt. ltd. is a providing 60 days Project training at Verilog . Training will be perform in the evening at the scheduled time .

Benefits from training :-

1:- Complete knowledge of Verilog with projects .
2:- Every participant will get training certificate + project handling certificate after complete training .

Fee :- 1100/- (INR)

Participate student will get daily documentation and video files lectures .

Total seats :- 100

Query session :-

Daily a query session will be organized By skype and gtalk user can talk to us and solves the problem .

Project :-

We will work at many minor and major projects during training session .
Name of some projects

1:- 32 bit floating point multiplication by single precision floating point multiplication
2:- Digital Clock
3:- Advanced Traffic Light control
4:- 16 bit Microprocessor

Please contact us at vlsiengitech@gmail.com or 09649955929 .

For more details visit at :-

http://www.vlsiengitech.com/verilog-online-training

AMS Verification Engineer NXP Semiconductors - Bangalore

Job description

• Define Verification strategies at different Abstraction Levels
• Define and Develop Verification Infrastructure for Mixed Signal Chips
• Develop Verification Test Plan
• Develop Analog models
• Write and execute Test Cases
• Post Silicon Validation
• Develop Core Competence in AMS Verification
• Coach juniors

Desired Skills and Experience

• Verified Analog and Mixed Signal blocks
• Analog Blocks Modeling ( Verilog-A, Verilog –AMS)
• Vehicle Networking knowledge ( CAN,LIN, Ethernet Protocols, Switches)
• Automotive Industry Awareness
• Verilog Expert and basic knowledge of VHDL
• Good Digital Verification experience
• Familiar with HVL like System C, UVM
• Masters/Bachelors in Electronics

Apply Now

Digital Design Intel - Bangalore , KA

Job description

INTERNSHIP DETAILS

Intel is inviting applicantions for its digital design internship programme.

About Intel (http://www.intel.com/):

Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in California. Intel is one of the world's largest and highest valued semiconductor chip makers, based on revenue.It is the inventor of the x86 series of microprocessors, the processors found in most personal computers

About the Internship:

Responsibilities may be quite diverse of an exempt technical nature.

Who can apply:

Candidate should be pursuing masters degree in either Electronics, VLSI, embedded system, or microelectronics from reputed institutes.

Streams: Electronics and Communication Engineering, Microelectronics, VLSI Design and Embedded system
Additional Information:

Please Note: The start date of the internship has not been mentioned in the official post.

Apply Now

Engineer - IC Design Broadcom - Bangalore , KA

Job description

Job Description

.We need motivated and highly experienced design engineers with the ability to carry blocks from concept to silicon. You should have good exposure to micro-architecture, logic design, timing closure and post silicon support activities.
The selected candidates will be responsible for VLSI/Chip Design for 802.11 wireless chips & involves SOC/Phy/MAC Architecture, RTL Design, implementation, Verification, Synthesis, P&R, Timing Closure, STA, low power design for 802.11 wireless chips.

Job Requirements 

The candidate should meet the following requirements.
• 1+ years of experience in frontend VLSI design with BSEE/MSEE
• Experience in micro-architecture/logic design of complex blocks and subsystems, with ability to work with multiple teams to define specification and lead the design effort.
• Experience in Verilog/VHDL design, analysis and verification of DSP functions, Developing block level micro-architecture of DSP blocks from algorithms specified in C
• Expertise in ASIC/FPGA design flows including simulators, functional and code coverage tools, lint/CDC analysis, synthesis, stating timing analysis, power estimation and related tools
• Experience in creating self-generating / self-checking simulation & verification environment using C, HDL, Perl, TCL, Python scripts
• Experience in ARM subsystem, Top-Level Chip Interconnect Architectures, Clocking Scheme, PMU Architecture, Power Topology
• Experience for any of the following domains is desirable - 802.11 WLAN Chip/Phy/MAC designs, or other related wireless technologies
• Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams
• Highly motivated and independent contributor

Country 

India

State/Province 

India Cities

City/Town 

Bangalore

Shift 

1st Shift - Day

Percent of Travel Required 

5% - 10%

Function 

Engineering

Discipline 

IC Design

Alternate Location(s) 

N/A

Apply Now

Design Engineer - SC ARM - Bangalore , KA

Job description

Job Description

Introduction :ARM offers IC designers a wide range of choices from its broad portfolio of standard cell, memory, and I/O products. The ARM product line is optimized for each silicon technology. ARM's Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM products have been used in circuits running as fast as 2GHz+ and are in production or development at 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 28nm, 20nm and 14 nm semiconductor processes for various foundries and IDMs.
Our circuit group comprises some of the industry's leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital circuit professional to work with a very successful circuit and layout team. The team has exposure to a wide variety of design rules from leading edge foundries as well as design teams from many of the world's leading developers of digital ICs making for an ideal learning environment.
Job Purpose :The Standard Cell Design Engineer will be responsible for the development of standard cell libraries in a wide variety of different processes targeting all extremes of power, performance, and density. The Standard Cell Design Engineer will work as part of a small team to optimize schematics, develop layout, drive the mask design team, characterize the cells, generate all standard library views, and verify all views by exercising them using a variety of industry standard tool flows.
Accountabilities / Responsibilities :

• Circuit design of standard cells including traditional logic cells as well as advanced power management cells
• Verification of functionality, performance & power of developed circuits
• Characterization of the Cell library
• Generation of all views delivered with our Physical IP product lines
• Testing of all views by exercising them in several industry standard design flows
• Good understanding of layout to effectively drive the mask design team and perform layout development tasks
• Understanding of deep submicron device physics in order to account for these non-ideal effects during cell design
• Understanding or an ability to learn a wide variety of industry standard modelling formats including:Liberty (CCS and NLM), Verilog, LEF, Milkyway, Spice, ECSM, and CDB

Education & Qualifications: 

• Qualified candidates will have a university degree(s) in Electronic Engineering, Computer Engineering or other relevant technical discipline.
• Experience developing or utilizing standard cell libraries.

Job Requirements 

Essential Skills & ExperienceSpecifically, candidates should have:

• An understanding of MOSFET electrical characteristics
• An understanding of power, performance, and area tradeoffs
• Understanding of layout at the transistor level
• Understanding of Design For Manufacturability (DFM) layout techniques
• Experience with transistor level circuit simulators
• Experience with Schematic and Layout Capture: Cadence schematic or equivalent.
• Experience with backend verification tools: DRC, LVS (HERCULES, CALIBRE, ICV)
• Experience with LEF and Milkyway view formats
• Understanding of extraction methodologies and limitations
• Diagnostic skills for tools and resultant reports
• Knowledge of shell/tcl/Perl scripting
• Basic Source control management with tool such DesignSync

Skills & ExperienceOther relevant skills include:

• Modeling Languages: Verilog, VHDL.
• Basic Experience with EDA tools such as Design Compiler, PrimeTime, Modelsim, EDIS, ICC, Talus
• An understanding of transistor level device physics
• Understanding and preferably experience with transistor level design of static circuits including state retaining elements like latches and flops

Interpersonal Skills: It is essential for the successful applicant to:

• Co-operate & communicate well with library development team
• Proficient in English with good communication skills, oral and written
• Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the design center's success
• Demonstrate a positive attitude and respect for all members of the team
• Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems

Apply Now

Memory Design Engineer 3D-IP Semiconductors - Bengaluru Area, India

Job description

For our Memory team we are hiring candidates with 3-8 years' experience in Memory Development. The role is Memory Architecture Design and Characterization in advance process technology nodes (65nm/45nm/28nm and lower process technologies )

Below are the details of  the position:

• Designation : Design Engg/Senior Design Engg/Team Leader
• Experience :  3-8 years' in Memory Development (SRAM/FLASH)
• Qualification : B.E/B.Tech/M.Tech/M.S/M.E in VLSI, Electrical or Electronics Engineering
• Location : Bangalore

Desired Skills and Experience

1. Memory Architect

• 3-8 years' experience in the development of SRAM Memory Compilers, embedded Flash Memory
• Expertise in Memory Architecture design, Critical Path schematic design, Sense Amplifier design, BitCell design.
• Experience in latest process nodes such as 28nm and lower.  
• Knowledge of Timing, Marginalities, Low power issues is a must
• Knowledge of layout issues in different Memory architectures
• Knowledge of Cadence/Synopsys/Mentor EDA tools is a must
• Knowledge of scripting languages such as Shell, Peril is a plus

       2.  Memory Characterization

• 3-8 years' experience in the development of SRAM Memory Compilers
• Hands on experience in Memory Characterization for latest process technology nodes (65nm/45nm/28nm) 
• Expertise in writing Timing definitions(setup, hold, cycle times, etc.) and Marginalities
• Hands on experience in generating and verification of views such as.LIB, VITAL, LEF, etc.
• Knowledge of Perl/Shell Programming is a plus

Apply Now

Mixed Signal SOC Integrator NXP Semiconductors - Bangalore

Job description

•Responsible for  Analog Mixed signal Chip Level Integration
•Digital and Analog IP Integration  in Mixed Signal Designs
•Top level Dft Infrastructure and tool flow
•Functional and Test IO Muxing
•DfT insertion and validation
•Develop basic test cases for ensuring RTL Integrity
•Automation for Integration
•Strong understanding of Revision Control tools and Configuration Management
•experience with Design database management (collabnet, Synchronisity or likewise)
•release strategy Way of Working, tagging etc
•IP incoming inspections
•RTL Quality Checks using  Lint, CDC  etc
•RTL Synthesis, Constraints development
•Equivalence Checking
•supporting Backend/Physical design
•Power analysis
•Contribute in audits/reviews and work with team and Chip Architect & PM to achieve timely and high quality deliverables

Desired Skills and Experience

•Greater than 10  years of   Relevant experience  with at least 3 years of experience as  Chip  Integration Lead
•Experience in Integrating Complex Mixed Signal Chips
•In-depth Understanding  of  Mixed Signal Chips  architecture
•Strong Coding skills in VHDL and  Verilog
•Preferably experienced with Cadence tooling,
•Synthesis at Chip Level,
•Worked with multi-power domain designs and experience with low power methodologies and flows
•Scan Insertion
•Good Knowledge  of DFT , Mentor DfT tools
•  Synthesis and PT- SI timing analysis for complex blocks and working through timing ECO fixes
•Worked on RTL and gate-level simulations and debug.
•Worked with multi clock, rail and high speed designs.
•Worked with physical design team for timing closure.
•Bring in some unique expertise

Apply Now

Business Development Engineer Global Marketing Services, India - Bengaluru Area, India

Job description

         

         

         

The job involves understanding semiconductor and microelectronic fabrication and assembly processes and discuss with prospective customers to match their requirements with the tools and materials we offer. The candidate main objective is to win business and would be required to demonstrate and install simple equipments like to photoresist spinners, thickness measurement tools, etc as and when required. The candidate should be ready to travel to any location in India and also travel to Vendor's location outside for product training if required.

Desired Skills and Experience

         

         

         

Prefer candidates with BE or ME in Electronics with a specialization in Microelectronics or VLSI. Candidates with prior experience in selling semiconductor process tools would be preferred but not a must. Candidates must have knowledge on electronic circuits assembly and hands on experience would be preferred. Candidates with some past experience in selling and especially to govt institutes would be given preference.

Apply now

ASIC / VLSI - Staff Engineer, Timing & Synthesis Semtech - Bhubanswar

Job description

Responsibilities:

Candidate will be responsible for synthesis & STA setup, full chip timing analysis, timing eco closure. Responsibilities also include supporting backend design team to tape out of the full chip. Candidate should also possess excellent communication skills to interact with external customers and cross site teams within company. Candidate will get an opportunity to work in RTL development and micro-architecture of digital blocks

Desired Skills and Experience

Requirements:

• Expertise in Synthesis, Static timing analysis and Equivalence
• Checking (LEC) using synopsys/cadence tools.
• Experience in timing constraints development & validation is a must.
• Experience in developing & validating the functional & test-mode timing constraints is also must.
• Familiarity with ASIC design flows for deep sub-micron technologies. 40nm and 28nm will be preferable. 
• Knowledge of DFT/ATPG/MBIST will be a plus point.
• Any exposure to Synopsys Lynx flow will be preferable.
• Knowledge of RTL design and functional simulation will be preferable.

Apply Now

Senior Application Engineer DFT - 2736 Mentor Graphics - Bangalore , KA

Job description

Description

Company: Mentor Graphics
Job Title: Senior Application Engineer DFT - 2736
Job Location: India - Bangalore
Job Category: Sales 

Job Duties: 
1. As part of the customer support team, help grow customer satisfaction with Mentor’s DFT tools by helping them successfully deploy Automatic Test Pattern Generation (ATPG) and Built In Self-Test (BIST) tools (such as Fastscan, TestKompress, MemoryBIST, LogicBIST, BoundaryScan, SOCScan).

2. Work on service requests to deliver excellent technical support in a timely manner to Mentor’s customers

3. Recognize and communicate potential business opportunities to support the growth of Mentor’s business

4. Work collaboratively with field applications engineers, account teams and engineering to successfully deploy Mentor’s products and services

5. Some Travel would be required in this position.

6. Help the account team in growing the business by increasing adoption of Mentor DFT technology at customers.

7. Deliver training on Mentor’s DFT tools and flows to customers

Job Qualifications: 
1. As a member of the technical sales team, you will contribute to our success by helping customers deploy Mentor’s DFT tools efficiently. This is a challenging position that will assist in growing the DFT business in India. You will workclosely with customers as well as field applications and engineering teams.

2. Need excellent communication and problem solving skills, program management skills, hands-on and a self-starter, able to work independently but still build relationships withManagers and with customers.

3. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability.

4. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies is required.

5. Preferred experience in specific areas: Operating Systems: UNIX, Linux, Sun Solaris.

Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.

CAD Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Logic BIST flows and methodologies is a plus.

6. Three to ten years of design experience in DFT solution implementation, and a good understanding of backend design. Experience in Memory BIST and Logic BIST implementation will be a big plus.

7. Education: Bachelors in Electrical Engineering (min). Masters in Electrical Engineering is a plus

Apply Now

SENIOR PHYSICAL DESIGN ENGINEER NVIDIA - Bangalore , KA

Job description

SENIOR PHYSICAL DESIGN ENGINEER

Job ID

1687219

Location

India, Bangalore

Description

SENIOR PHYSICAL DESIGN ENGINEER #1687219

RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets
- Participating in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification

MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- 4+ years of experience in large VLSI physical design implementation on 40nm, 28nm or 20nm technology
- Successful track record of delivering designs to production is a must
- Experience leading small teams (3-5) is a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (ICC/DC/PT/STAR-RC), Cadence (First Encounter)
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions
- Proficiency using Perl, Tcl, Make scripting is preferred

Apply now

TEST ENGINEER HCL Technologies - Bangalore , KA

Job description

Job Description (Posting).

To test the VLSI Code as per work allocated within the quality standards prescribed so as to meet the product requirements

Experience 

3-5 Years

Qualification 

BE/BTech

No. of Positions 

0

Skill (Primary) 

Technical Skills-Hardware & ASIC-VHDL

Removal Date 

14-Oct-2014

Apply Now

MASK DESIGN ENGINEER- Full-custom Layout SanDisk - Bengaluru Area, India (1-3 yr exp)

Job description

Experience : 1 to 3 Years

Good Understanding of Basic VLSI Concepts
Good understanding of CMOS process
Knowledge of Verification tools (DRC/LVS tools like Hercules, Assura, Calibre etc...)
Experience in Cadence Platform (layout/layoutXL)
Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM
Understanding of Standard cell/Macro development
Scripting knowledge a plus: PERL and SKILL
Good communication skills

Desired Skills and Experience

Standard cell/Macro development
Support block layouts like Charge Pumps, IO_PADS, Reference generators and other analog blocks of NAND chip
Person will be working with our India and US physical design teams for all tasks

Apply Now

Asic Design Engineer Avago Technologies - IN-KA-Bangalore

Job description

VLSI Technical engineer with 6-10 years of experience in RTL Design Activities 



He/she should have strong knowledge of following 

Ø Verilog RTL/System Verilog coding 

Ø SoC integration flows ( integrating multiple IPs and associated, Understanding of Power Management ( voltage domain, power domains, clock domains ) 

Ø Synthesis ( DC ) and Timing Concepts

Ø Spyglass ( lint, DFT, PM, CLK/RST, CDC) 

Ø Formal Verification( LEC) 

Ø Perl scripting 

CAD Tools : Synopsys 



Domain : Ethernet ,PICe or any networking protocol 



Education Qualification/Yr of experience: Bachelors/Master’s in Electronics/Computer Engg 


Qualifications
Education Qualification/Yr of experience: Bachelors/Master’s in Electronics/Computer Engg

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Hardware Engineer - VLSI/Embedded (4-8 yrs) hirist.com - Delhi Ncr , DL

Job description

Position - Hardware Engineer

Candidate Qualifications

- 4+ Years Industry experience in Front End VLSI Design, Development and Implementation using FPGAs

- Require FPGA based product architecture experience in Networking Domain (switches and routers)

- Experience in Embedded System Projects

- Team Lead experience of entire product life cycle based on FPGA, including System Architecture, Partitioning, RTL Design and Coding, IP Integration, Verification, Synthesis, Timing Constraints and Analysis, Timing Optimization, Debugging, Place and Route and On-target Verification.

- Expert skills in RTL coding using VHDL and Verilog

- Experience in High performance design/integration including Multi-Gigabit Transceivers, DDR2/DDR3 memory controllers.

- Well versed with FPGA Devices from Xilinx and Altera and their architecture, development tools (Quartus-II / ISE / Vivado), Front End Verification tools, Soft-processors like NIOS-II / Microblaze, Bus Protocols, Chipscope / SignalTap

- Experience with FPGA board schematic entry, Partitioning, Component selection, Interface design, board bring-up using tools like Oscilloscope/ Logic Analyzer and on-board functionality testing

- Knowledge of C/C++, protocols like TCP/IP and Linux operating system internals

- Experience in scripting tools like Perl, Python

Education

Bachelor’s/ Master's degree - Electronics and Communication

Job Description

- Trading Product Design and Development

- Design of hardware accelerated platform to capture & process real-time Market Data feeds to compute data for strategies to execute orders with pre trade risk management, over various gateways utilizing FPGAs as well as other high-performance technologies. Includes Price feed handler, Order book generation, Execution Gateways and other time critical components of the system

- Design for low latency and high throughput

- Design for scalability, integration of multiple markets and multiple strategies

- Network Infrastructure Design

- System Deployment and Operations

- System and Network Performance Monitoring and Analytics for ultra low latency

Apply Now

FPGA Verification Engineer Parker Hannifin - Bangalore , KA

Job description

Job Description :

PARKER AEROSPACE 

Parker Aerospace, an operating segment of Parker Hannifin Corporation, is one of the world’s leading producers of flight control, hydraulic, fuel, inerting, fluid conveyance, thermal management, and engine systems and components for the aerospace industry. We design and build equipment for virtually every aircraft and aero engine being produced in the world today.

In addition to game-changing technology, our customers look to us for shorter lead times, lower costs, higher reliability, and lifetime support. All coupled with the positive attitude and innovative thinking of a true business partner.

Parker Aerospace provides unmatched performance for both our customers and shareholders, built on a foundation of integrity, innovation, and customer satisfaction. As a result, our business has seen consistent growth and, best of all, our team members share in Parker’s success.

ENGINEER II – FPGA VERIFICATION 

SUMMARY
Responsible for design, verification and certification of aerospace firmware. Responsibilities will include requirements creation, validation, conceptual design, detail design and testing. Position to be based in Bangalore, India.

RESPONSIBILITIES
· Create control circuits, design (writing of VHDL), develop timing constraints, simulate (functional and timing), place and route synthesized designs.
· Perform supplier oversight of tasks, artifacts/deliverables and quality of the work-products to ensure all required data items and artifacts to support FAA SIO audits are correct and complete.
· Create and verify that simulation test cases, procedure and test bench follow Parker development standards (independent reviews, checklist, etc.). Verify test cases/procedure/test bench are created to satisfy existing design requirements.
· Participate in peer design reviews and support continuous process improvements.
· Provide interface between India team and US team.
Job Requirements :

QUALIFICATIONS
· Bachelor Degree (BS) in Electrical Engineering or related technical discipline. Master’s Degree is a plus. Ability to perform the essential functions of the job typically acquired through 2-3 years of related experience.
· Experience in the design, development and certification of aerospace firmware. Specific experience in DO-254 certification required. Specific experience in motor drive and flight control applications is a plus. Experience with ARINC-429, CAN, SPI or other serial interfaces.
· Experience in requirements capture and validation. Experience with VHDL design and verification. Experience with Xilinx and Altera development tools.
· Experience with ModelSim/QuestaSim to perform simulation and debug of VHDL design. Experience with in-circuit verification techniques. Possess excellent trouble shooting skills and knowledgeable in Chipscope / Signal Tap FGPA debugging tools. Experience creating simulation/verification test bench using VHDL language.
· Experience in supporting FAA SOI audits. Leadership experience a plus.
· Strong technical writing, verbal and written communication skills. Excellent work ethic. Able to work well in teams (local as well as remote) and is self-motivated.

Apply now

Microprocessor Verification Engineer IBM - Bangalore

Job description

Individual will be responsible for performing design verification for POWER & System Z microprocessors and subsystems. Primary responsibilities include creating verification test plans and environments on several machine platforms, the ability to learn and use world class verification tools for high-end designs, and the ability in debug and triage of defects found through verification processes. This position requires collaboration across multiple teams including logic design, various verification teams focusing all the way from unit to chip and system level, and processor and system architecture teams. Applicant should have proficiency in object oriented programming using languages such as C++ and SystemVerilog, experience in scripting languages such as Perl, working knowledge of hardware description language (HDL) (VHDL or Verilog), computer architecture, experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc. , and demonstrated communication skills (written and oral).

IBM stands apart from all competitors in that it can leverage the end to end stack in implementing POWER and Z systems. The foundry, design teams, firmware and software stack are all contained within the company, allowing IBM to deliver a fully integrated solution. IBM POWER dominates the UNIX market and now has its sights set on accomplishing the same in Linux. System Z dominates the mainframe market and is growing with Linux offerings and delivering near 0 downtime enterprise computing to emerging countries.

The Watson supercomputer is built exclusively on POWER processors. This new ecosystem allows POWER to play an exciting role across many industries including healthcare, transportation, and business analytics as new customers from different industries continue to line up to have Watson tackle their toughest problems.

IBM has announced the OpenPOWER Consortium, partnering IBM Power with other IT companies to leverage architectures unique to POWER to deliver increased value to customers.

In addition, POWER and System Z is aggressively shifting focus to Cloud computing and can leverage software acquisitions in this emerging space to make IBM the rising competitor in Cloud.

We are designing next generation microprocessors to be integral to solving these important challenges for both POWER Systems and System Z.

We are looking for top talent, come join our team!

Required
PhD/Master's/ Bachelor's Degree in Engineering
Experience - 5 - 10 Years
Basic knowledge in Verification (simulation, formal, or emulation). Skills Needed: Processor/Computer Architecture Knowledge, Programming Skills (such as C++/UVM/SV/Perl), Understanding of HDL (VHDL/Verilog)
English: Fluent

Required

• Bachelor's Degree
• At least 5 years experience in System Verilog/C++ / OOP Skills, VHDL/Verilog,
• Basic knowledge in Verification (simulation, formal, or emulation)
• English: Fluent

Preferred

• Master's Degree in Engineering
• At least 6 years experience in System Verilog/C++ / OOP Skills, VHDL/Verilog,

IBM is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status.

Apply now

Engineer, Principal - IC Design Broadcom - Bangalore , KA

Job description

Job Description

We need motivated and highly experienced design engineers with the ability to carry blocks from concept to silicon. The candidate should have good exposure to micro-architecture, logic design, timing closure and post silicon support activities.
The selected candidates will be responsible for VLSI/Chip Design for 802.11 wireless chips & involves SOC/Phy/MAC Architecture, RTL Design, implementation, Verification, Synthesis, P&R, Timing Closure, STA, low power design for 802.11 wireless chips.

Key Requirements
The candidate should meet the following requirements.
• 10 + years of experience in frontend VLSI design with BSEE/MSEE
• Experience in micro-architecture/logic design of complex blocks and subsystems, with ability to work with multiple teams to define specification and lead the design effort.
• Experience in Verilog/VHDL design, analysis and verification of DSP functions, Developing block level micro-architecture of DSP blocks from algorithms specified in C
• Expertise in ASIC/FPGA design flows including simulators, functional and code coverage tools, lint/CDC analysis, synthesis, stating timing analysis, power estimation and related tools
• Experience in creating self-generating / self-checking simulation & verification environment using C, HDL, Perl, TCL, Python scripts
• Experience in ARM subsystem, Top-Level Chip Interconnect Architectures, Clocking Scheme, PMU Architecture, Power Topology
• Experience for any of the following domains is desirable - 802.11 WLAN Chip/Phy/MAC designs, or other related wireless technologies
• Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams
• Highly motivated and independent contributor

Job Requirements 

We need motivated and highly experienced design engineers with the ability to carry blocks from concept to silicon. The candidate should have good exposure to micro-architecture, logic design, timing closure and post silicon support activities.
The selected candidates will be responsible for VLSI/Chip Design for 802.11 wireless chips & involves SOC/Phy/MAC Architecture, RTL Design, implementation, Verification, Synthesis, P&R, Timing Closure, STA, low power design for 802.11 wireless chips.

Key Requirements
The candidate should meet the following requirements.
• 10 + years of experience in frontend VLSI design with BSEE/MSEE
• Experience in micro-architecture/logic design of complex blocks and subsystems, with ability to work with multiple teams to define specification and lead the design effort.
• Experience in Verilog/VHDL design, analysis and verification of DSP functions, Developing block level micro-architecture of DSP blocks from algorithms specified in C
• Expertise in ASIC/FPGA design flows including simulators, functional and code coverage tools, lint/CDC analysis, synthesis, stating timing analysis, power estimation and related tools
• Experience in creating self-generating / self-checking simulation & verification environment using C, HDL, Perl, TCL, Python scripts
• Experience in ARM subsystem, Top-Level Chip Interconnect Architectures, Clocking Scheme, PMU Architecture, Power Topology
• Experience for any of the following domains is desirable - 802.11 WLAN Chip/Phy/MAC designs, or other related wireless technologies
• Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams
• Highly motivated and independent contributor

Country 

India

State/Province 

India Cities

City/Town 

Bangalore

Shift 

1st Shift - Day

Percent of Travel Required 

None

Function 

Engineering

Discipline 

IC Design

Alternate Location(s) 

N/A

Apply now