Job description
Description
Company: Mentor Graphics
Job Title: Senior Application Engineer DFT - 2736
Job Location: India - Bangalore
Job Category: Sales
Job Duties:
1. As part of the customer support team, help grow customer satisfaction with Mentor’s DFT tools by helping them successfully deploy Automatic Test Pattern Generation (ATPG) and Built In Self-Test (BIST) tools (such as Fastscan, TestKompress, MemoryBIST, LogicBIST, BoundaryScan, SOCScan).
2. Work on service requests to deliver excellent technical support in a timely manner to Mentor’s customers
3. Recognize and communicate potential business opportunities to support the growth of Mentor’s business
4. Work collaboratively with field applications engineers, account teams and engineering to successfully deploy Mentor’s products and services
5. Some Travel would be required in this position.
6. Help the account team in growing the business by increasing adoption of Mentor DFT technology at customers.
7. Deliver training on Mentor’s DFT tools and flows to customers
Job Qualifications:
1. As a member of the technical sales team, you will contribute to our success by helping customers deploy Mentor’s DFT tools efficiently. This is a challenging position that will assist in growing the DFT business in India. You will workclosely with customers as well as field applications and engineering teams.
2. Need excellent communication and problem solving skills, program management skills, hands-on and a self-starter, able to work independently but still build relationships withManagers and with customers.
3. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability.
4. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies is required.
5. Preferred experience in specific areas: Operating Systems: UNIX, Linux, Sun Solaris.
Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.
CAD Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Logic BIST flows and methodologies is a plus.
6. Three to ten years of design experience in DFT solution implementation, and a good understanding of backend design. Experience in Memory BIST and Logic BIST implementation will be a big plus.
7. Education: Bachelors in Electrical Engineering (min). Masters in Electrical Engineering is a plus
Company: Mentor Graphics
Job Title: Senior Application Engineer DFT - 2736
Job Location: India - Bangalore
Job Category: Sales
Job Duties:
1. As part of the customer support team, help grow customer satisfaction with Mentor’s DFT tools by helping them successfully deploy Automatic Test Pattern Generation (ATPG) and Built In Self-Test (BIST) tools (such as Fastscan, TestKompress, MemoryBIST, LogicBIST, BoundaryScan, SOCScan).
2. Work on service requests to deliver excellent technical support in a timely manner to Mentor’s customers
3. Recognize and communicate potential business opportunities to support the growth of Mentor’s business
4. Work collaboratively with field applications engineers, account teams and engineering to successfully deploy Mentor’s products and services
5. Some Travel would be required in this position.
6. Help the account team in growing the business by increasing adoption of Mentor DFT technology at customers.
7. Deliver training on Mentor’s DFT tools and flows to customers
Job Qualifications:
1. As a member of the technical sales team, you will contribute to our success by helping customers deploy Mentor’s DFT tools efficiently. This is a challenging position that will assist in growing the DFT business in India. You will workclosely with customers as well as field applications and engineering teams.
2. Need excellent communication and problem solving skills, program management skills, hands-on and a self-starter, able to work independently but still build relationships withManagers and with customers.
3. Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability.
4. Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies is required.
5. Preferred experience in specific areas: Operating Systems: UNIX, Linux, Sun Solaris.
Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.
CAD Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Logic BIST flows and methodologies is a plus.
6. Three to ten years of design experience in DFT solution implementation, and a good understanding of backend design. Experience in Memory BIST and Logic BIST implementation will be a big plus.
7. Education: Bachelors in Electrical Engineering (min). Masters in Electrical Engineering is a plus
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