Job description
Position - Hardware Engineer
Candidate Qualifications
- 4+ Years Industry experience in Front End VLSI Design, Development and Implementation using FPGAs
- Require FPGA based product architecture experience in Networking Domain (switches and routers)
- Experience in Embedded System Projects
- Team Lead experience of entire product life cycle based on FPGA, including System Architecture, Partitioning, RTL Design and Coding, IP Integration, Verification, Synthesis, Timing Constraints and Analysis, Timing Optimization, Debugging, Place and Route and On-target Verification.
- Expert skills in RTL coding using VHDL and Verilog
- Experience in High performance design/integration including Multi-Gigabit Transceivers, DDR2/DDR3 memory controllers.
- Well versed with FPGA Devices from Xilinx and Altera and their architecture, development tools (Quartus-II / ISE / Vivado), Front End Verification tools, Soft-processors like NIOS-II / Microblaze, Bus Protocols, Chipscope / SignalTap
- Experience with FPGA board schematic entry, Partitioning, Component selection, Interface design, board bring-up using tools like Oscilloscope/ Logic Analyzer and on-board functionality testing
- Knowledge of C/C++, protocols like TCP/IP and Linux operating system internals
- Experience in scripting tools like Perl, Python
Education
Bachelor’s/ Master's degree - Electronics and Communication
Job Description
- Trading Product Design and Development
- Design of hardware accelerated platform to capture & process real-time Market Data feeds to compute data for strategies to execute orders with pre trade risk management, over various gateways utilizing FPGAs as well as other high-performance technologies. Includes Price feed handler, Order book generation, Execution Gateways and other time critical components of the system
- Design for low latency and high throughput
- Design for scalability, integration of multiple markets and multiple strategies
- Network Infrastructure Design
- System Deployment and Operations
- System and Network Performance Monitoring and Analytics for ultra low latency
Candidate Qualifications
- 4+ Years Industry experience in Front End VLSI Design, Development and Implementation using FPGAs
- Require FPGA based product architecture experience in Networking Domain (switches and routers)
- Experience in Embedded System Projects
- Team Lead experience of entire product life cycle based on FPGA, including System Architecture, Partitioning, RTL Design and Coding, IP Integration, Verification, Synthesis, Timing Constraints and Analysis, Timing Optimization, Debugging, Place and Route and On-target Verification.
- Expert skills in RTL coding using VHDL and Verilog
- Experience in High performance design/integration including Multi-Gigabit Transceivers, DDR2/DDR3 memory controllers.
- Well versed with FPGA Devices from Xilinx and Altera and their architecture, development tools (Quartus-II / ISE / Vivado), Front End Verification tools, Soft-processors like NIOS-II / Microblaze, Bus Protocols, Chipscope / SignalTap
- Experience with FPGA board schematic entry, Partitioning, Component selection, Interface design, board bring-up using tools like Oscilloscope/ Logic Analyzer and on-board functionality testing
- Knowledge of C/C++, protocols like TCP/IP and Linux operating system internals
- Experience in scripting tools like Perl, Python
Education
Bachelor’s/ Master's degree - Electronics and Communication
Job Description
- Trading Product Design and Development
- Design of hardware accelerated platform to capture & process real-time Market Data feeds to compute data for strategies to execute orders with pre trade risk management, over various gateways utilizing FPGAs as well as other high-performance technologies. Includes Price feed handler, Order book generation, Execution Gateways and other time critical components of the system
- Design for low latency and high throughput
- Design for scalability, integration of multiple markets and multiple strategies
- Network Infrastructure Design
- System Deployment and Operations
- System and Network Performance Monitoring and Analytics for ultra low latency
No comments:
Post a Comment