Job description
VLSI Technical engineer with 6-10 years of experience in RTL Design Activities
He/she should have strong knowledge of following
Ø Verilog RTL/System Verilog coding
Ø SoC integration flows ( integrating multiple IPs and associated, Understanding of Power Management ( voltage domain, power domains, clock domains )
Ø Synthesis ( DC ) and Timing Concepts
Ø Spyglass ( lint, DFT, PM, CLK/RST, CDC)
Ø Formal Verification( LEC)
Ø Perl scripting
CAD Tools : Synopsys
Domain : Ethernet ,PICe or any networking protocol
Education Qualification/Yr of experience: Bachelors/Master’s in Electronics/Computer Engg
Qualifications
Education Qualification/Yr of experience: Bachelors/Master’s in Electronics/Computer Engg
He/she should have strong knowledge of following
Ø Verilog RTL/System Verilog coding
Ø SoC integration flows ( integrating multiple IPs and associated, Understanding of Power Management ( voltage domain, power domains, clock domains )
Ø Synthesis ( DC ) and Timing Concepts
Ø Spyglass ( lint, DFT, PM, CLK/RST, CDC)
Ø Formal Verification( LEC)
Ø Perl scripting
CAD Tools : Synopsys
Domain : Ethernet ,PICe or any networking protocol
Education Qualification/Yr of experience: Bachelors/Master’s in Electronics/Computer Engg
Qualifications
Education Qualification/Yr of experience: Bachelors/Master’s in Electronics/Computer Engg
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