Job description
•Responsible for Analog Mixed signal Chip Level Integration
•Digital and Analog IP Integration in Mixed Signal Designs
•Top level Dft Infrastructure and tool flow
•Functional and Test IO Muxing
•DfT insertion and validation
•Develop basic test cases for ensuring RTL Integrity
•Automation for Integration
•Strong understanding of Revision Control tools and Configuration Management
•experience with Design database management (collabnet, Synchronisity or likewise)
•release strategy Way of Working, tagging etc
•IP incoming inspections
•RTL Quality Checks using Lint, CDC etc
•RTL Synthesis, Constraints development
•Equivalence Checking
•supporting Backend/Physical design
•Power analysis
•Contribute in audits/reviews and work with team and Chip Architect & PM to achieve timely and high quality deliverables
•Digital and Analog IP Integration in Mixed Signal Designs
•Top level Dft Infrastructure and tool flow
•Functional and Test IO Muxing
•DfT insertion and validation
•Develop basic test cases for ensuring RTL Integrity
•Automation for Integration
•Strong understanding of Revision Control tools and Configuration Management
•experience with Design database management (collabnet, Synchronisity or likewise)
•release strategy Way of Working, tagging etc
•IP incoming inspections
•RTL Quality Checks using Lint, CDC etc
•RTL Synthesis, Constraints development
•Equivalence Checking
•supporting Backend/Physical design
•Power analysis
•Contribute in audits/reviews and work with team and Chip Architect & PM to achieve timely and high quality deliverables
Desired Skills and Experience
•Greater than 10 years of Relevant experience with at least 3 years of experience as Chip Integration Lead
•Experience in Integrating Complex Mixed Signal Chips
•In-depth Understanding of Mixed Signal Chips architecture
•Strong Coding skills in VHDL and Verilog
•Preferably experienced with Cadence tooling,
•Synthesis at Chip Level,
•Worked with multi-power domain designs and experience with low power methodologies and flows
•Scan Insertion
•Good Knowledge of DFT , Mentor DfT tools
• Synthesis and PT- SI timing analysis for complex blocks and working through timing ECO fixes
•Worked on RTL and gate-level simulations and debug.
•Worked with multi clock, rail and high speed designs.
•Worked with physical design team for timing closure.
•Bring in some unique expertise
•Experience in Integrating Complex Mixed Signal Chips
•In-depth Understanding of Mixed Signal Chips architecture
•Strong Coding skills in VHDL and Verilog
•Preferably experienced with Cadence tooling,
•Synthesis at Chip Level,
•Worked with multi-power domain designs and experience with low power methodologies and flows
•Scan Insertion
•Good Knowledge of DFT , Mentor DfT tools
• Synthesis and PT- SI timing analysis for complex blocks and working through timing ECO fixes
•Worked on RTL and gate-level simulations and debug.
•Worked with multi clock, rail and high speed designs.
•Worked with physical design team for timing closure.
•Bring in some unique expertise
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