Job description
Experience : 1 to 3 Years
Good Understanding of Basic VLSI Concepts
Good understanding of CMOS process
Knowledge of Verification tools (DRC/LVS tools like Hercules, Assura, Calibre etc...)
Experience in Cadence Platform (layout/layoutXL)
Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM
Understanding of Standard cell/Macro development
Scripting knowledge a plus: PERL and SKILL
Good communication skills
Desired Skills and Experience
Standard cell/Macro development
Support block layouts like Charge Pumps, IO_PADS, Reference generators and other analog blocks of NAND chip
Person will be working with our India and US physical design teams for all tasks
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